The present invention generally relates to a layer structure having a contact hole suitable for dynamic random access memories having fine contact holes, and a method of producing such a layer structure. More particularly, the present invention is concerned with a fin-shaped capacitor having such a layer structure, and a method of forming such a fin-shaped capacitor. Furthermore, the present invention is concerned with a dynamic random access memory having such a fin-shaped capacitor.
Recently, there has been considerable activity as regards the development of 64Mbit dynamic random access memories (DRAM). There are known DRAMs having three-dimensional stacked capacitor cells capable of providing a storage capacity equal to or higher than 64Mbits (see Japanese Laid-Open Patent Application Nos. 1-137666, 1-147857 and 1-154549, U.S. Pat. No. 4,974,040 and T. Ema et al., "3-DIMENSIONAL STACKED CAPACITOR CELL FOR 16M AND 64M DRAMS", International Electron Devices Meetings, 592-IEDM 88, Dec. 11-14, 1988). In order to increase the integration density, it is necessary to reduce the two-dimensional size of each memory cell without reducing the capacitance of each stacked capacitor.
In order to fabricate 64Mbit DRAMs, a feature scale approximately equal to 0.3 [.mu.m] is required. However, the conventional photolithography technique can realize a feature scale approximately equal to a maximum of 0.5 [.mu.m]. 64Mbit DRAMs can be realized by reducing the size of each storage (stacked) capacitor. For this purpose, it is necessary to reduce the size of a contact window (opening) for a storage electrode which is a part of the stacked capacitor. As described above, since the feature scale realized by the conventional photolithography technique is approximately 0.5 [.mu.m], it is impossible to form the contact window having a size approximately equal to 0.3 [.mu.m]. It is also necessary to reduce the size of a window (contact hole) provided for connecting a word line formed of, for example, polysilicon, and a low-resistance wiring line (word-line shunt layer) formed of Al or Al alloy, directed to preventing the occurrence of a delay in signal transmission in the word line.
Japanese Laid-Open Patent Application No. 63-119239 discloses a method for forming a fine pattern narrower than a feature scale limit of the conventional photolithography technique. The application teaches a process in which polysilicon, PSG or SiO.sub.2 is grown on an SiO.sub.2 mask having a window through which a substrate is partially exposed, and a grown film on the mask and the exposed substrate surface is anisotropically etched, so that a sidewall is formed on the substrate so that it is formed around the entire inner wall of the window in the mask. The distance between opposite surfaces of the sidewall in the window is less than the feature scale limit. Thus, a surface area of the substrate less than the feature scale limit is exposed through the sidewall in the window. Then, the substrate is etched in such a way that the combination of the sidewall and the mask function as an etching mask, so that a hole is formed in the substrate.
The above-mentioned Patent Application discloses an arrangement in which the mask is formed of SiO.sub.2 and a member to be processed is formed of Si. Thus, the removal of the mask material can be easily made. However, when a multilayer structure, such as DRAMS, is produced, it is necessary to consider three layers of a mask material, a material to be processed and a underlying material which is located under the processed material and which is exposed through a hole formed in the processed material. In this case, it is necessary to prevent the exposed portion of the underlaying material from be damaged during a process in which the mask material is removed. Further, if the mask material is left in the finalized products, it is necessary to have no problem arising from the existence of the left mask material. The above-mentioned Japanese Application does not suggest the above matters.
Japanese Laid-Open Patent Application No. 60-224218 discloses the use of a sidewall directed to providing a window (contact hole) smaller than the feature scale limit of the conventional photolithography technique. The sidewall is formed of Al and formed on an SiO.sub.2 layer and around an inner wall of a window formed in a silicon nitride (Si.sub.3 N.sub.4) layer also formed on the SiO.sub.2 layer. The SiO.sub.2 layer is selectively etched in such a way that the Al sidewall and the Si.sub.3 N.sub.4 layer function as mask layers. However, it is very difficult to form the Al sidewall in contact with the inner wall of the window in the Si.sub.3 N.sub.4 layer, since Al has a poor coverage characteristic. Further, it is necessary to form the Si.sub.3 N.sub.4 layer which is sufficiently thick, because the selective etching ratio of Si.sub.3 N.sub.4 to SiO.sub.2 is small.
Japanese Laid-Open Patent Application No. 63-116430 (which corresponds to U.S. patent application Ser. No. 924,223 filed on Oct. 28, 1986) teaches the use of a sidewall for forming a hole smaller than the scale limit of the conventional photolithgraphy technique. The just above application shows a lift-off process for removing the mask material. However, the lift-off process has a problem in that some of the mask material separated from the substrate is re-adhered hereto. This frequently causes a pattern fault in a subsequent process. The Japanese application of concern does not disclose an effective step to process the mask material. Further, the Japanese application shows a sidewall formed on the side surface of a photosensitive material. It is necessary to form the sidewall at a low temperature due to the thermal stability of the photosensitive material. Thus, there is a great limitation regarding the selection of mask materials. In addition, the structure shown in the Japanese application of concern is limited to a special application.